FIG. 1 illustrates a conventional output circuit for a digital circuit. To simplify discussion, this application will assume that the digital circuit is a memory circuit; however, it should be understood that the invention described herein applies to any circuit which outputs data. Data lines 11a, 11b . . . 11n each receive a respective data bit DQ0, DQ1 . . . DQn from a memory core, and provide the respective data bits to respective output buffer latches 13a, 13b . . . 13n which in turn deliver the latched output data DQ0, DQ1 . . . DQn to a plurality of output data lines 15a, 15b . . . 15n. The output buffer latches 13a, 13b . . . 13n are clocked by a clock signal which originates from a clock source 17 and is provided to the output buffer latches 13a, 13b . . . 13n in common, either directly from clock source 17, or through a delay circuit 19. The clock signal applied to the output buffer latches 13a, 13b . . . 13n causes the output buffers to latch in data from the data lines 11a, 11b . . . 11n and make it available on the output lines 15a, 15b . . . 15n for a period of time know as the data hold time, commonly referred to as toh.
As shown in FIG. 2 a first clock cycle is used to synchronize a READ operation which causes the data DQ0, DQ1 . . . DQn to be delivered from a memory core to the lines 11a, 11b . . . 11n and a subsequent clock cycle T1 causes the output buffers to latch and hold the data on lines 11a, 11b . . . 11n for the data hold time. The time the data DQ0, DQ1 . . . DQn is accessed from memory locations and during which it is made available on lines 11a, 11b . . . 11n is commonly referred to as memory access time, tac.
Referring back to FIG. 1, a delay circuit 19 is often employed to ensure that data is available on all of the data input lines 11a, 11b . . . 11n before the output buffers latch and hold the data.
As the speed of digital circuits continues to increase there are ever increasing demands placed on the timing circuitry for memory devices due to shorter clock periods. In addition, the very complex circuitry of modern digital circuits, e.g., memory devices, often leads to clock signal lines being routed to the output buffer latches 13, 13b . . . 13n with unequal circuit path lengths both inside a chip and/or outside a chip in the chip packaging. As a consequence of these signal path length differences, and other timing aberrations caused by circuit topology within a chip, at higher clocking speeds, it is becoming increasingly difficult to time align the data across all the output lines 15a, 15b . . . 15c of a memory device.